This invention relates to circuitry constructed from complementary field effect transistors which exhibit negative resistance characteristics. More particularly the invention is a Complementary Symmetry Metal-Oxide-Semiconductor Field-Effect Transistor (CMOS-FET) circuit substitute for a Programmable Unijunction Transistor (PUT).
Negative resistance devices have wide application as switching devices and are typically formed as discrete circuit elements and are conventionally charge controlled devices. Certain negative resistance circuit elements such as the PUT, however, may be formed as a composite of bipolar transistors. PUT's are commonly used as discrete circuit elements, but when required on an integrated circuit (IC) can be formed by interconnecting the collector and base electrodes of a pnp transistor respectively to the base and collector electrodes of an npn transistor. One of the collector-base interconnections serves as a control electrode for a principal conduction path between the emitter electrodes of the two transistors.
Bipolar IC's are classically manufactured on P-type semiconductor substrate material. IC's fabricated with technologies to provide CMOS-FET's (e.g., for digital-circuit applications) on the other hand are commonly manufactured on N-type substrate material and, in some instances, with Silicon-on-Sapphire (SOS) material. The use of these N-type and SOS substrate materials imposes severe limitations on the concomitant integration of complementary bipolar transistors suitable for producing PUT's on CMOS-FET IC's. Although operable lateral-type bipolar transistors can be fabricated on these substrate materials, they have characteristics which limit their usefulness, i.e., low forward current gain and relatively low gain-bandwidth product. Furthermore, lateral-type bipolar transistors fabricated on N-type substrate material with process-compatible CMOS-FET's are prone to spurious parasitic SCR-type latch-up. Additionally, the overdriven (saturated) operation of bipolar transistors connected in PUT configurations limits their operational speeds as a consequence of their inherent storage time.